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Resetting a counter

:: EPE Chat Zone ­:: ­Radio Bygones Message Board :: » EPE Forum Archives 2005-2006 » Archive through 28 June, 2006 » Resetting a counter « Previous Next »

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Mike_b
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Username: Mike_b

Post Number: 219
Registered: 05-2005

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Posted on Monday, 26 June, 2006 - 05:49 pm:   Edit Post Delete Post Print Post

I have a 4 bit counter 4015, but I want it to count when clocked only up to 4 (not 16) and then start.

Good ... so I decide to check Q0 and Q1 with a NAND gate, pass this through an inverter, which drives the reset line.

I double check my design on a simulator. The simulator shows a very narrow spike when Q0 and Q1 are high, after which, of course, the counter correctly resets.

Where am I going wrong please? Is this spike 'real' or is it the simulator?. Any ideas how I avoid this spike if it is real.

thanks

rgds
mb
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Epithumia
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Username: Epithumia

Post Number: 9
Registered: 06-2006

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Posted on Tuesday, 27 June, 2006 - 09:48 am:   Edit Post Delete Post Print Post

Hi Mike,

I'm not sure you've given the right part number. According to the Texas website 4015 is a shift register, not a counter.

Apart from that, the narrow spike you describe sounds like an asynchronous reset - the counter does not wait for a clock before resetting. As soon as the reset goes active the counter resets, removing the reset - all in a few nanoseconds. Sounds as if you need to feed back Q2 instead.

If you really want to gate Q0 and Q1 AND have the counter stay in the '11' state for a whole clock then you want to look for a chip with a synchronous reset input, such as 74HC163.
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Mike_b
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Username: Mike_b

Post Number: 221
Registered: 05-2005

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Posted on Tuesday, 27 June, 2006 - 10:04 am:   Edit Post Delete Post Print Post

Epit ... sorry .. it was a 4520.

Thanks very much .. I get it now.

rgds

mb

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